The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2016
Filed:
Oct. 02, 2014
Cadence Design Systems, Inc., San Jose, CA (US);
Tsair-Chin Lin, Saratoga, CA (US);
Jingbo Gao, San Jose, CA (US);
Yevgen Ryazanov, San Jose, CA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
Essential information for system operations, memory analysis, and design signal analysis is captured while a hardware based verification platform is performing emulation and testing. This recorded information is then accessible via a memory device and can be used to perform offline debugging with a virtual verification machine (VVM). Users can then release the shared resources and run operation commands to control replay of the design test or emulation in offline mode. Users can access any point in time of the recorded emulation in order to perform detailed design analysis and debugging operations. Offline analysis and debugging may include running certain design cycles, rerunning the emulation until the design reaches a certain state, evaluating memory contents in the design, evaluating design signals for any node in the design, etc.