The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Apr. 07, 2015
Seok-hoon Kim, Suwon-si, KR;
Jin-bum Kim, Seoul, KR;
Kwan-heum Lee, Suwon-si, KR;
Byeong-chan Lee, Yongin-si, KR;
Cho-eun Lee, Pocheon-si, KR;
Su-jin Jung, Hwaseong-si, KR;
Seok-hoon Kim, Suwon-si, KR;
Jin-bum Kim, Seoul, KR;
Kwan-heum Lee, Suwon-si, KR;
Byeong-chan Lee, Yongin-si, KR;
Cho-eun Lee, Pocheon-si, KR;
Su-jin Jung, Hwaseong-si, KR;
Abstract
Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.