The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Dec. 23, 2011
Applicants:

Kenneth Shoemaker, Los Altos Hills, CA (US);

Paul Fahey, Campbell, CA (US);

Inventors:

Kenneth Shoemaker, Los Altos Hills, CA (US);

Paul Fahey, Campbell, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/04 (2006.01); G11C 11/406 (2006.01); G06F 1/20 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40626 (2013.01); G06F 1/206 (2013.01); G11C 5/025 (2013.01); G11C 7/04 (2013.01); G11C 11/406 (2013.01); G11C 11/40615 (2013.01); G11C 2211/4067 (2013.01);
Abstract

Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.


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