The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Oct. 14, 2008
Richard West, Easton, MA (US);
Puneet Zaroo, Santa Clara, CA (US);
Carl A. Waldspurger, Palo Alto, CA (US);
Xiao Zhang, Rochester, NY (US);
Haoqiang Zheng, Sunnyvale, CA (US);
Richard West, Easton, MA (US);
Puneet Zaroo, Santa Clara, CA (US);
Carl A. Waldspurger, Palo Alto, CA (US);
Xiao Zhang, Rochester, NY (US);
Haoqiang Zheng, Sunnyvale, CA (US);
VMware, Inc., Palo Alto, CA (US);
Abstract
Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread. In another embodiment, cache miss-rate curves are constructed for a thread to help analyze performance tradeoffs when changing cache allocations of the threads in the system.