The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Aug. 06, 2013
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Huaxiang Yin, Beijing, CN;

Xiaolong Ma, Beijing, CN;

Weijia Xu, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/30604 (2013.01); H01L 29/66795 (2013.01); H01L 29/7853 (2013.01); H01L 29/7854 (2013.01); H01L 21/823431 (2013.01);
Abstract

A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.


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