The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Apr. 10, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih-Guo Shen, New Taipei, TW;

Wei-Min Tseng, New Taipei, TW;

Chien-Chung Wang, New Taipei, TW;

Huey-Chi Chu, Hsin-Chu, TW;

Wen-Chuan Chiang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/31053 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/64 (2013.01); H01L 23/642 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 23/5226 (2013.01);
Abstract

The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.


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