The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2016
Filed:
Jan. 20, 2015
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
David A. DeMuynck, Underhill, VT (US);
Zhong-Xiang He, Essex Junction, VT (US);
Daniel R. Miga, St. Albans, VT (US);
Matthew D. Moon, Jeffersonville, VT (US);
Daniel S. Vanslette, Fairfax, VT (US);
Eric J. White, Charlotte, VT (US);
Assignee:
GlobalFoundries, Inc., Grand Cayman, KY;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76843 (2013.01); H01L 21/76802 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76879 (2013.01); H01L 23/5227 (2013.01); H01L 28/10 (2013.01); H01L 2924/0002 (2013.01);
Abstract
The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.