The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Jul. 27, 2015
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Hwong-Kwo Lin, Santa Clara, CA (US);

Lei Wang, Santa Clara, CA (US);

Spencer Gold, Westford, MA (US);

Zhenye Jiang, Santa Clara, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 11/419 (2006.01); G11C 11/417 (2006.01); G11C 29/02 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 11/417 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01); G11C 11/4076 (2013.01);
Abstract

An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.


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