The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Oct. 07, 2014
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Russell Segal, Sunnyvale, CA (US);

Peiqing Zou, San Jose, CA (US);

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/505 (2013.01); G06F 17/5031 (2013.01); G06F 17/5036 (2013.01); G06F 17/5045 (2013.01); G06F 17/5072 (2013.01); G06F 2217/06 (2013.01); G06F 2217/62 (2013.01); G06F 2217/84 (2013.01);
Abstract

Systems and techniques for determining a set of timing paths for creating a circuit abstraction are described. During operation, an embodiment can receive a set of circuit elements in the circuit design that are candidates for optimization. Next, the embodiment can determine a set of timing paths by identifying critical timing paths in the circuit design whose delay is affected by a change in an input capacitance of a circuit element in the set of circuit elements. The embodiment can then identify a set of side loads based on the set of timing paths, and can create the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during optimization of the circuit element.


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