The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Jun. 28, 2013
Applicants:

Harish K. Krishnamurthy, Beaverton, OR (US);

George E. Matthew, Hillsboro, OR (US);

Bharani Thiruvengadam, Beaverton, OR (US);

Inventors:

Harish K. Krishnamurthy, Beaverton, OR (US);

George E. Matthew, Hillsboro, OR (US);

Bharani Thiruvengadam, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03K 5/13 (2014.01); H03K 7/08 (2006.01); H03L 7/081 (2006.01); H02M 3/158 (2006.01); G06F 1/32 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/13 (2013.01); G06F 1/324 (2013.01); G06F 1/3265 (2013.01); H02M 3/158 (2013.01); H03K 7/08 (2013.01); H03L 7/0818 (2013.01); H03K 2005/00019 (2013.01);
Abstract

Described is a pulse width modulation architecture for high speed digitally controlled voltage regulator. Described is an apparatus which comprises: a first phase interpolator (PI) for coupling an input to a delay element of a delay line, wherein the coupling is via a selection unit; a second PI for coupling an output of the delay element of the delay line, wherein the coupling is via the selection unit; and a third PI for providing an output, the third PI calibrated according to delay settings of the first and second PIs.


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