The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Mar. 03, 2015
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Chieh Cheng, Hsinchu, TW;

Shih-Guei Yan, Hsinchu, TW;

Wen-Jer Tsai, Hsinchu, TW;

Nan-Heng Lu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8239 (2006.01); H01L 27/105 (2006.01); H01L 29/792 (2006.01); H01L 27/115 (2006.01); H01L 21/266 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7926 (2013.01); H01L 21/266 (2013.01); H01L 23/528 (2013.01); H01L 27/11568 (2013.01);
Abstract

A memory device includes a substrate, a first doped region, composite structures, word lines, and a charge storage layer. The first doped region is disposed on a surface of the substrate. The composite structures are disposed on the first doped region. Each composite structure includes two semiconductor fin structures and a dielectric layer. Each semiconductor fin structure includes a second doped region disposed at an upper portion of the semiconductor fin structure and a body region disposed between the second doped region and the first doped region. The dielectric layer is disposed between the semiconductor fin structures. The word lines are disposed on the substrate. Each word line covers a partial sidewall and a partial top of each composite structure. The charge storage layer is disposed between the composite structures and the word lines.


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