The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Jun. 23, 2015
Applicant:
Mie Fujitsu Semiconductor Limited, Kuwana, Mie, JP;
Inventors:
Dalong Zhao, San Jose, CA (US);
Pushkar Ranade, Los Gatos, CA (US);
Bruce McWilliams, Menlo Park, CA (US);
Assignee:
Mie Fujitsu Semiconductor Limited, Kuwana, Mie, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/8238 (2006.01); H01L 21/82 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/02367 (2013.01); H01L 21/82 (2013.01); H01L 21/823878 (2013.01);
Abstract
Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.