The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Aug. 26, 2015
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01); H01L 21/8222 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/28088 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/32133 (2013.01); H01L 21/8222 (2013.01); H01L 21/823412 (2013.01); H01L 29/4966 (2013.01); H01L 29/66333 (2013.01); H01L 29/66363 (2013.01);
Abstract
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.