The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Mar. 17, 2015
Applicant:

Toshiba Corporation, Tokyo, JP;

Inventors:

Yongxiang He, Sunnyvale, CA (US);

Xinyu Zhang, Palo Alto, CA (US);

Assignee:

Toshiba Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3213 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/47 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/32133 (2013.01); H01L 21/0254 (2013.01); H01L 21/28581 (2013.01); H01L 21/32134 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42316 (2013.01); H01L 29/475 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01);
Abstract

A P-N junction gate high electron mobility transistor (HEMT) device with a self-aligned gate structure and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a heterojunction comprising a barrier layer formed on a channel layer. A gate layer is formed on the barrier layer, the gate layer comprising a P-type group III-V semiconductor material suitable for depleting the carriers of a current conducting channel at the heterojunction when the HEMT device is off. A gate electrode comprising indium tin oxide (ITO) is formed on the gate layer, the gate electrode and the gate layer having substantially the same length.


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