The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

May. 14, 2013
Applicant:

Kyushu Institute of Technology, Fukuoka, JP;

Inventors:

Yasuo Sato, Fukuoka, JP;

Senling Wang, Fukuoka, JP;

Kohei Miyase, Fukuoka, JP;

Seiji Kajihara, Fukuoka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31721 (2013.01); G01R 31/3177 (2013.01); G01R 31/318541 (2013.01); G01R 31/318575 (2013.01);
Abstract

The purpose of the invention is to provide a fault detection system etc., that reduces shift power in scan-out while maintaining the fault coverage. The fault detection system configured to detect a fault in a logic circuit by means of a scan test, includes: multiple flip-flops; a final signal generation unit that generates a final signal indicating a final capture in a capture mode; an assignment unit that differs from the logic circuit and the flip-flops, and that sets a logic signal for a part of the flip-flops upon receiving the final signal; and a fault detection device that detects a fault by making a comparison between a test output captured from the logic circuit and including the logic value set by the assignment unit and a test output to be obtained when the logic circuit has no fault and including the logic value set by the assignment unit.


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