The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
Nov. 22, 2013
Applicant:
Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano, JP;
Inventor:
Teruaki Chino, Nagano, JP;
Assignee:
SHINKO ELECTRIC INDSTRIES CO., LTD., Nagano-shi, Nagano, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/10 (2006.01); H05K 3/40 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4007 (2013.01); H01L 21/4853 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49894 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H05K 3/3436 (2013.01); H05K 3/3473 (2013.01); H05K 2201/0338 (2013.01);
Abstract
There is provided a wiring substrate. The wiring substrate includes: a wiring pattern of an outermost layer; a solder resist layer having an opening portion therein, wherein a portion of the wiring pattern is exposed through the opening portion, and the exposed portion of the wiring pattern is defined as a connection pad; and a solder bump on the connection pad. The connection pad includes: a solder layer; and a metal post that is entirely covered by the solder layer, wherein a portion of the solder layer is interposed between the connection pad and the metal post.