The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Dec. 19, 2014
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Mitchell G. Poplack, San Jose, CA (US);

Simon Sabato, Saratoga, CA (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H04L 1/00 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0041 (2013.01); G06F 11/10 (2013.01);
Abstract

In one form a method of encoding a data word for serial transmission is provided, where a data word comprising a plurality of data bits is received, an invert bit having a bit value is appended to the data word, the data bits and invert bit are scrambled, ECC check bits are generated, and the data bits, invert bit, and ECC check bits are shuffled together to form an encoded word to be transmitted from a transmitter. A receiver may decode by implementing a decode process with error correction. The encoded word may also be DC balanced by checking the disparity of the bits to be encoded against a running disparity to invert or not the bits. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may implement the disclosed encoding/decoding for interconnections between emulation chips.


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