The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Mar. 25, 2015
Applicants:

Sung Gi Hur, Hwaseong-si, KR;

Taeyong Kwon, Suwon-si, KR;

Sangsu Kim, Yongin-si, KR;

Jungdal Choi, Hwaseong-si, KR;

Inventors:

Sung Gi Hur, Hwaseong-si, KR;

TaeYong Kwon, Suwon-si, KR;

Sangsu Kim, Yongin-si, KR;

Jungdal Choi, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 23/31 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7849 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 27/0886 (2013.01);
Abstract

A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.


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