The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
Sep. 11, 2015
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/367 (2006.01); H01L 23/053 (2006.01); H01L 25/065 (2006.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/56 (2013.01); H01L 23/053 (2013.01); H01L 23/49541 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 24/49 (2013.01); H01L 24/85 (2013.01); H01L 25/065 (2013.01); H01L 2924/15158 (2013.01);
Abstract
A multi-component integrated circuit (IC) package has a base component (e.g., an interposer) defining a base of the IC package, a plurality of die pads extending from the base and forming side walls of the IC package, one or more IC dies, each mounted on an interior surface of one of the die pads, and bond wires electrically connecting the IC dies to another component of the IC package, such as the interposer or another die. By mounting dies on non-horizontal side walls, the IC package can provide more-effective thermal dissipation than conventional 3D IC packages having stacks of IC dies.