The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Apr. 15, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Tong-Yu Chen, Hsinchu, TW;

Kuo-Yuh Yang, Hsinchu County, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02664 (2013.01); H01L 21/26506 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/30625 (2013.01); H01L 21/76232 (2013.01); H01L 21/76283 (2013.01); H01L 29/0649 (2013.01); H01L 21/7624 (2013.01); H01L 21/76898 (2013.01);
Abstract

A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.


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