The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
May. 29, 2015
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Po-Nien Chen, Miaoli County, TW;
Bao-Ru Young, Hsinchu County, TW;
Chi-Hsun Hsieh, Taichung, TW;
Harry Hak-Lay Chuang, Singapore, SG;
Wei Cheng Wu, Hsinchu County, TW;
Eric Huang, Miaoli County, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region.