The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9378323 B1

Date of Patent:

Jun. 28, 2016

Filed:

Dec. 08, 2014

Methods for retargeting vias and for fabricating semiconductor devices with retargeted vias

Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventor:

Ayman Hamouda, Fishkill, NY (US);

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:

Ingrassia Fisher & Lorenz, P.C.

Primary Examiner:

Caleen Sullivan

Int. Cl.

CPC ...

G06F 17/50 (2006.01); G03F 7/20 (2006.01); H01L 21/768 (2006.01); H01L 23/544 (2006.01);

U.S. Cl.

CPC ...

G06F 17/5077 (2013.01); G03F 7/70433 (2013.01); G03F 7/70625 (2013.01); G03F 7/70633 (2013.01); G06F 17/5081 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 23/544 (2013.01);

Abstract

Methods for retargeting a via and for fabricating a semiconductor device with a retargeted via are provided. In one embodiment, a method for retargeting a via includes drawing a lower metal layer shape, drawing a via shape for overlying the lower metal layer shape, and drawing an upper metal layer shape for overlying the via shape to create an interconnection area between the via shape and the upper metal layer shape. The method includes determining a potential area loss of the interconnection area during integrated circuit fabrication processing. The method further includes enlarging the via shape to compensate for the potential area loss.

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