The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
Feb. 11, 2010
Mahesh U. Wagh, Tacoma, WA (US);
Wilfred W. Kwok, Markham, CA (US);
Sridhar Muthrasanallur, Turnwater, WA (US);
Mahesh U. Wagh, Tacoma, WA (US);
Wilfred W. Kwok, Markham, CA (US);
Sridhar Muthrasanallur, Turnwater, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a 'retry' event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the 'available' amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.