The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
Jul. 26, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Alexander Gendler, Kiriat Motzkin, IL;
George Leifman, Haifa, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 12/08 (2016.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3206 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 1/3225 (2013.01); G06F 11/34 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 2212/1028 (2013.01); Y02B 60/1225 (2013.01);
Abstract
In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed.