The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Mar. 28, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Moshe Teplitsky, Tel-Aviv, IL;

Michael Genossar, Modiin, IL;

Elan Banin, Raanana, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01); H04B 1/30 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0045 (2013.01); H04B 1/30 (2013.01); H04B 2001/305 (2013.01); Y02B 60/50 (2013.01);
Abstract

Logic for direct current (DC) estimation of a wireless communication packet. Logic may determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet. Logic may determine a second DC estimation based upon a second set of sequences in the preamble. Logic may select one of the DC estimations based upon a frequency-offset estimation. Logic may remove one of the DC estimations from the packet. Logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias. And logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.


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