The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Nov. 19, 2014
Applicant:

United Microelectronics Corporation, Hsinchu, TW;

Inventors:

Jhen-Cyuan Li, New Taipei, TW;

Shui-Yen Lu, Tainan, TW;

Man-Ling Lu, Gueishan Township, TW;

Yu-Cheng Tung, Kaohsiung, TW;

Chung-Fu Chang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/161 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02118 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/31116 (2013.01); H01L 21/31138 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted-symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.


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