The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2016
Filed:
Sep. 29, 2014
Samsung Electronics Co., Ltd., Suwon-si, KR;
JinBum Kim, Seoul, KR;
Jungho Yoo, Seongnam-si, KR;
Byeongchan Lee, Yongin-si, KR;
Choeun Lee, Pocheon-si, KR;
Hyun Jung Lee, Suwon-si, KR;
Seong Hoon Jeong, Seongnam-si, KR;
Bonyoung Koo, Suwon-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.