The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Nov. 06, 2012
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Daniel Asher Cohen, Los Gatos, CA (US);

John LeRoy Pierce, Temple, NH (US);

Petr William Spacek, Princeton, MA (US);

Prasanna Prithviraj Rao, Boston, MA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06N 5/00 (2006.01); G06F 11/26 (2006.01); G06F 11/263 (2006.01); G06F 17/11 (2006.01);
U.S. Cl.
CPC ...
G06N 5/003 (2013.01); G06F 17/5022 (2013.01); G06F 11/261 (2013.01); G06F 11/263 (2013.01); G06F 17/11 (2013.01);
Abstract

The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design. The method may also include associating, using the at least one computing device, an identifier with each constraint solver call utilized in a simulation of the electronic design. The method may also include generating, using the at least one computing device, an application programming interface configured to allow a user to navigate through electronic design simulation results based upon, at least in part, the identifier associated with each constraint solver call.


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