The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Dec. 22, 2011
Applicants:

Kuo-lang Tseng, Cupertino, CA (US);

Baohong Liu, Cupertino, CA (US);

Ritu Sood, Milpitas, CA (US);

Manohar Ruben Castelino, Sunnyvale, CA (US);

Madhukar Tallam, Fremont, CA (US);

Inventors:

Kuo-Lang Tseng, Cupertino, CA (US);

Baohong Liu, Cupertino, CA (US);

Ritu Sood, Milpitas, CA (US);

Manohar Ruben Castelino, Sunnyvale, CA (US);

Madhukar Tallam, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/14 (2006.01); G06F 9/455 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1441 (2013.01); G06F 9/45558 (2013.01); G06F 12/0292 (2013.01); G06F 12/1458 (2013.01); G06F 2009/45587 (2013.01);
Abstract

Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are described. In some embodiments, a system detects an indication of an attempt by the instruction to write to the protected memory region. In addition, the system determines if the instruction is allowed to write to the protected memory region based on a starting address and data length of the instruction. Furthermore, if the instruction is allowed to write to the protected memory region, the system updates the protected memory region with the instruction results.


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