The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2016
Filed:
Dec. 27, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Debendra Das Sharma, Saratoga, CA (US);
Mohan J. Kumar, Aloha, OR (US);
Balint Fleischer, Groton, MA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 11/20 (2006.01); G06F 12/08 (2016.01); G06F 15/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1088 (2013.01); G06F 11/2043 (2013.01); G06F 11/2087 (2013.01); G06F 11/2092 (2013.01); G06F 11/2097 (2013.01); G06F 12/08 (2013.01); G06F 12/0837 (2013.01); G06F 15/16 (2013.01); G06F 11/108 (2013.01); G06F 12/0833 (2013.01);
Abstract
An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.