The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jan. 28, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yi-Fang Li, Changhua County, TW;

Chun-Sheng Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/148 (2006.01); H01L 29/768 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66606 (2013.01); H01L 29/51 (2013.01); H01L 29/66636 (2013.01);
Abstract

The present disclosure provides a semiconductor structure, including a substrate, a metal gate, a dielectric layer, and an etch stop layer. The metal gate is positioned on the substrate and possesses a first surface. The dielectric layer surrounds the metal gate and possesses a second surface. The etch stop layer is in contact with both the first surface and the second surface. The first surface is higher than the second surface. The present disclosure also provides a method for manufacturing a semiconductor structure, including forming a dummy gate on a substrate; forming a second etch stop layer over the dummy gate; forming a dielectric layer over the dummy gate; replacing the dummy gate with a metal gate; etching back the dielectric layer to form a second surface of the dielectric layer lower than a first surface of the metal gate; and forming a first etch stop layer over the metal gate and the dielectric layer.


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