The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jan. 29, 2015
Applicant:

Sumitomo Electric Device Innovations, Inc., Yokoahama-shi, JP;

Inventors:

Toshiyuki Kosaka, Yokohama, JP;

Hiroshi Kawakubo, Yokohama, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 21/268 (2006.01); H01L 21/306 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/268 (2013.01); H01L 21/30621 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/76898 (2013.01); H01L 29/2003 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01);
Abstract

A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the wafer including first and second scribe lines extending along first and second directions, respectively, (2) thinning the wafer, (3) forming a groove in a first scribe line excluding a region located in an outer peripheral portion of the wafer, the groove piercing the wafer from the first surface to a second surface opposite to the first surface to expose the adhesive, the first scribe line and the second scribe line demarcating chip regions; and (4) removing the adhesive by immersing the wafer adhered to the support substrate in a solvent such that the solvent permeates into the groove.


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