The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jan. 26, 2015
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Luca Milani, Mairano, IT;

Fabrizio Torricelli, Brescia, IT;

Anna Richelli, Brescia, IT;

Luigi Colalongo, Bertinoro, IT;

Zsolt Miklos Kovàcs-Vajna, Brescia, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0408 (2013.01); H01L 21/28273 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11558 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an electrically floating layer of conductive material defining a first capacitive coupling with the program/read portion and a second capacitive coupling with the erase portion. The first capacitive coupling defines a first capacitance greater than a second capacitance defined by the second capacitive coupling. The erase portion is configured so that an electric current extracts charge carriers from the electrically floating layer to store a first logic value in the memory cell. The program/read portion is further configured so that an electric current injects charge carriers in the electrically floating layer to store a second logic value in the memory cell.


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