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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9368168 B1

PDFFull Text
Date of Patent:
Jun. 14, 2016

Filed:

Sep. 16, 2015

Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Kyeong-Han Lee, Gyeonggi-do, KR;

Seok-Cheon Kwon, Gyeonggi-do, KR;

Dong-Yang Lee, Gyeonggi-do, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:

F. Chau & Associates, LLC

Primary Examiner:

Vanthu Nguyen

Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 16/32 (2006.01); G11C 7/22 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 7/10 (2013.01); G11C 7/106 (2013.01); G11C 7/1051 (2013.01); G11C 7/1066 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 16/32 (2013.01); G11C 7/1018 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 2207/107 (2013.01); G11C 2207/2281 (2013.01);
Abstract

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Find Patent Forward Citations

Lee, Kyeong-Han. (2016). Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same (U.S. Patent No. 9368168). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9368168

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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