The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Nov. 21, 2013
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Pravin Kumar Venkatesan, Santa Clara, CA (US);

Kashinath Prabhu, Bangalore, IN;

Makarand Shirasgaonkar, Pune, IN;

Wayne Dettloff, Cary, NC (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 5/14 (2006.01); G11C 7/10 (2006.01); G11C 7/04 (2006.01); G11C 11/4099 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G11C 7/04 (2013.01); G11C 7/1048 (2013.01); G11C 7/1051 (2013.01); G11C 7/1078 (2013.01); G11C 11/4099 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 2029/0409 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.


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