The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Apr. 01, 2015
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Mu-Ying Tsao, Changhua County, TW;

Wei-Ren Chen, Pingtung County, TW;

Assignee:

eMemory Technology Inc., Hsinchu Science Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 27/112 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 27/115 (2006.01); H01L 29/51 (2006.01); H01L 23/525 (2006.01); H01L 29/93 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 16/0408 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 27/11206 (2013.01); H01L 27/11529 (2013.01); H01L 27/11573 (2013.01); H01L 29/42368 (2013.01); H01L 29/512 (2013.01); H01L 29/7817 (2013.01); H01L 29/7835 (2013.01); H01L 23/5252 (2013.01); H01L 29/93 (2013.01);
Abstract

A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first oxide define (OD) region and a second oxide define (OD) region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.


Find Patent Forward Citations

Loading…