Method and apparatus for synchronizing circuits in an emulation system utilizing its serial interconnect network

Abstract

Clock distribution schemes in emulation systems are typically complex and use significant resources. The present disclosure is generally directed to clock distribution to emulation chips using a serial interconnect mesh. A clock distribution tree is overlayed on the emulation chips allocated to a user's circuit design, the tree branching from a root emulation chip using selected serial interconnections and covering each allocated emulation chip. The emulation chips can recover a clock from received serial signals. The delay associated with each interconnection is determined and used by configuration software when creating the distribution tree. To start emulation stepping synchronously, each emulation chip is configured to know its delay from the root emulation chip. A message is sent from the root emulation chip to each branch emulation chip triggering a timer to countdown a time until emulation is to begin, allowing the emulation chips to start stepping in lockstep.