The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Aug. 14, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert C. Swanson, Olympia, WA (US);

Mariusz Oriol, Gdynia, PL;

Janusz Jurski, Hillsboro, OR (US);

Piotr Sawicki, Gdansk, PL;

Robert W. Cone, Portland, OR (US);

William J. O'Sullivan, Hillsboro, OR (US);

Mariusz Stepka, Gdansk, PL;

Babak Nikjou, Tempe, AZ (US);

Madhusudhan Rangarajan, Round Rock, TX (US);

Pawel Szymanski, Gdansk, PL;

Piotr Kwidzinski, Folsom, CA (US);

Robert Bahnsen, Tacoma, WA (US);

Mallik Bulusu, Olympia, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 9/50 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2023 (2013.01); G06F 9/5027 (2013.01); G06F 9/5088 (2013.01); G06F 11/14 (2013.01); G06F 11/203 (2013.01); G06F 11/2028 (2013.01); G06F 11/2033 (2013.01); G06F 11/2035 (2013.01);
Abstract

Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.


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