The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9367329 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 14, 2016

Filed:

Dec. 29, 2011
Applicants:

Steven S. Chang, San Jose, CA (US);

Anshuman Thakur, Beaverton, OR (US);

Ramacharan Charan Sundararaman, Hillsboro, OR (US);

Ramon Matas, Portland, OR (US);

Inventors:

Steven S. Chang, San Jose, CA (US);

Anshuman Thakur, Beaverton, OR (US);

Ramacharan Charan Sundararaman, Hillsboro, OR (US);

Ramon Matas, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/24 (2006.01); G06F 15/177 (2006.01); G06F 9/44 (2006.01); G06F 1/24 (2006.01); G06F 11/07 (2006.01); G06F 13/14 (2006.01); G06F 15/80 (2006.01); G06F 12/08 (2016.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4405 (2013.01); G06F 9/4403 (2013.01); G06F 15/177 (2013.01); G06F 1/24 (2013.01); G06F 11/0724 (2013.01); G06F 12/0813 (2013.01); G06F 13/00 (2013.01); G06F 13/14 (2013.01); G06F 15/80 (2013.01);
Abstract

This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.


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