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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9362606 B1

PDFFull Text
Expired
Date of Patent:
Jun. 07, 2016

Filed:

Aug. 23, 2013

On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures

Applicants:

International Business Machines Corporation, Armonk, NY (US);

University of South Carolina, Columbia, SC (US);

Inventors:

Barbara S. Dewitt, Essex Junction, VT (US);

Essam Mina, South Burlington, VT (US);

B M Farid Rahman, West Columbia, SC (US);

Guoan Wang, Irmo, SC (US);

Assignees:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

UNIVERISTY OF SOUTH CAROLINA, Columbia, SC (US);

Attorneys:

Bryan Bortnick

Andrew M. Calderon

Roberts Mlotkowski Safran & Cole, P.C.

Primary Examiner:

Thomas J Hiltunen

Int. Cl.
CPC ...
H01P 3/08 (2006.01); G06F 17/50 (2006.01); H01L 23/66 (2006.01); H01P 11/00 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01P 3/081 (2013.01); G06F 17/5077 (2013.01); H01L 23/5222 (2013.01); H01L 23/66 (2013.01); H01P 3/082 (2013.01); H01P 11/003 (2013.01); H01L 2223/6627 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.

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Dewitt, Barbara. (2016). On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures (U.S. Patent No. 9362606). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9362606

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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