The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Jun. 18, 2014
Applicants:

Moaniss Zitouni, Gilbert, AZ (US);

Edouard D. DE Frésart, Tempe, AZ (US);

Pon Sung Ku, Gilbert, AZ (US);

Ganming Qin, Chandler, AZ (US);

Inventors:

Moaniss Zitouni, Gilbert, AZ (US);

Edouard D. de Frésart, Tempe, AZ (US);

Pon Sung Ku, Gilbert, AZ (US);

Ganming Qin, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); G06F 17/50 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); G06F 17/5009 (2013.01); G06F 17/5072 (2013.01); H01L 29/063 (2013.01); H01L 29/0696 (2013.01); H01L 29/0852 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/66734 (2013.01); H01L 29/7811 (2013.01);
Abstract

Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.


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