Method of fabricating a nonvolatile memory device with a vertical semiconductor pattern between vertical source lines

Abstract

A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.