The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Dec. 29, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Zhang Zufa, Singapore, SG;

Khee Yong Lim, Singapore, SG;

Quek Kiok Boone Elgin, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28282 (2013.01); H01L 29/4236 (2013.01); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

Integrated circuits are provided. An exemplary integrated circuit includes a source/drain region in a semiconductor substrate. The integrated circuit includes a charge storage structure overlying the semiconductor substrate and having a first sidewall overlying the source/drain region. The integrated circuit also includes a control gate overlying the source/drain region. Further, the integrated circuit includes a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate.


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