The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Mar. 12, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Rajni J. Aggarwal, Garland, TX (US);

Jau-Yuann Yang, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 21/266 (2006.01); H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 49/02 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/266 (2013.01); H01L 21/283 (2013.01); H01L 21/28035 (2013.01); H01L 21/32053 (2013.01); H01L 21/32133 (2013.01); H01L 21/823807 (2013.01); H01L 21/823828 (2013.01); H01L 27/092 (2013.01); H01L 28/20 (2013.01); H01L 29/4916 (2013.01);
Abstract

An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.


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