The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2016
Filed:
Dec. 10, 2013
Applicant:
Lam Research Corporation, Fremont, CA (US);
Inventors:
Nader Shamma, Cupertino, CA (US);
Bart van Schravendijk, Cupertino, CA (US);
Sirish Reddy, Hillsboro, CA (US);
Chunhai Ji, Portland, OR (US);
Assignee:
Lam Research Corporation, Fremont, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/311 (2013.01); H01L 21/02115 (2013.01); H01L 21/02164 (2013.01); H01L 21/02274 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31122 (2013.01); H01L 21/31138 (2013.01);
Abstract
Methods and apparatuses for multiple patterning using image reversal are provided. The methods may include depositing gap-fill ashable hardmasks using a deposition-etch-ash method to fill gaps in a pattern of a semiconductor substrate and eliminating spacer etching steps using a single-etch planarization method. Such methods may be performed for double patterning, multiple patterning, and two dimensional patterning techniques in semiconductor fabrication.