The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Jan. 26, 2015
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Luca Milani, Mairano, IT;

Fabrizio Torricelli, Brescia, IT;

Anna Richelli, Brescia, IT;

Luigi Colalongo, Bertinoro, IT;

Zsolt Miklos Kovàcs-Vajna, Brescia, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0408 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 21/28273 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11558 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 29/7883 (2013.01);
Abstract

A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control portion. The read portion and the control portion share an electrically floating layer of conductive material defining a first capacitive coupling with the read portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity greater than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current injects or extracts charge carriers into or from the electrically floating layer to store of a first logic value or a second logic value, respectively, in the memory cell.


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