The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Mar. 11, 2013
Applicant:

Adesto Technologies Corporation, Sunnyvale, CA (US);

Inventors:

Nad Edward Gilbert, Gilbert, AZ (US);

John Dinh, Dublin, CA (US);

John Ross Jameson, III, Menlo Park, CA (US);

Michael N. Kozicki, Phoenix, AZ (US);

Shane Charles Hollmer, Grass Valley, CA (US);

Assignee:

Adesto Technologies Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0002 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0073 (2013.01);
Abstract

Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction; and (ii) a sensing circuit coupled to at least one of the plurality of resistive memory cells, where the sensing circuit is configured to read a data state of the at least one resistive memory cell by application of a third voltage in the forward bias direction or the bias reverse direction.


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