The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Feb. 25, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Griselda Bonilla, Fishkill, NY (US);

Kaushik Chanda, San Jose, CA (US);

Ronald G. Filippi, Wappingers Falls, NY (US);

Stephan Grunow, Poughkeepsie, NY (US);

Naftali E. Lustig, Croton on Hudson, NY (US);

Andrew H. Simon, Fishkill, NY (US);

Ping-Chuan Wang, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/327 (2006.01); H01L 23/58 (2006.01); G01R 31/02 (2006.01); G01R 31/04 (2006.01); G01R 31/07 (2006.01);
U.S. Cl.
CPC ...
G01R 31/327 (2013.01); G01R 31/025 (2013.01); G01R 31/04 (2013.01); G01R 31/07 (2013.01); H01L 23/58 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.


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