The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2016
Filed:
Mar. 18, 2013
Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;
National Institute of Advanced Industrial Science and Technology, Tokyo, JP;
Shinsuke Harada, Tsukuba, JP;
Noriyuki Iwamuro, Tsukuba, JP;
Yasuyuki Hoshi, Matsumoto, JP;
Yuichi Harada, Matsumoto, JP;
FUJI ELECTRIC CO., LTD., Kawasaki-shi, JP;
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE, Tsukuba-shi, JP;
Abstract
An n-type SiC layer is formed on a front face of an n-type SiC substrate and plural p-type regions are selectively formed inside the n-type SiC layer. A p-type SiC layer is formed covering the surfaces of the n-type SiC layer and the p-type regions. An n-type region is formed inside the p-type SiC layer to be connected to the n-type SiC layer. An n-type source region and a p-type contact region are formed inside the p-type SiC layer, positioned away from the n-type region and in contact with each other. The n-type region in the p-type SiC layer is formed such that the width Lof the n-type region is within a range from 0.8 μm to 3.0 μm and the impurity concentration of the n-type region is greater than 1.0×10cmand less than or equal to 5.0×10cm.