The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Sep. 26, 2014
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Ming Cheng, San Jose, CA (US);

Ken Wang, Milpitas, CA (US);

Tian Tian, Milpitas, CA (US);

Mohammad Ayyash, San Jose, CA (US);

Tuyen Pham, San Jose, CA (US);

Brian Rush, Southlake, TX (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/16 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/16 (2013.01); H01L 24/49 (2013.01); H01L 23/3107 (2013.01); H01L 23/49555 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48647 (2013.01); H01L 2224/48747 (2013.01); H01L 2224/48847 (2013.01); H01L 2924/12 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/14 (2013.01);
Abstract

A surface mount semiconductor package, semiconductor device, and method for fabrication of the surface mount semiconductor package and electrical device are described that include a leadframe assembly, an integrated circuit device disposed on the leadframe assembly, a silicon shield disposed on the integrated circuit device, where the silicon shield is configured to mitigate packaging stress to the integrated circuit device, and a molding layer that encapsulates the integrated circuit device, the silicon shield, and at least a portion of the leadframe assembly.


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